The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
For example, in integrated circuit designs (e.g., system-on-a-chip (or SOC), central processing units (CPU), or graphics processing units (GPU)), using standard cells (e.g., inverters, NAND, NOR, AND, OR, or flip-flops) has been a popular choice for its ease of handling complex designs. In these devices, metallization layers are formed over transistors and are used for routing signals and power lines (e.g., Vdd and ground) among the transistors. As the scaling down process continues, designing and fabricating such devices have encountered some challenges. For example, shrinking the geometry of power and/or ground lines typically increases the resistance thereof, which increases the power consumption of the devices. Also, placing signal lines closer in order to increase the design density typically increases coupling capacitance among the signal lines, which adversely impacts the performance of the devices. Accordingly, improvements in these areas are desired.